1. Field of the Invention
The present invention relates to a method for the selective formation of a silicide on a slice of semiconductor material (wafer) comprising exposed regions to be silicided and exposed regions not to be silicided.
The invention is applicable especially in the fabrication of MOS (Metal Oxide Semiconductor) transistors in all technologies that use silicides, particularly 0.18-μm, 0.12-μm, 90-nm or 65-nm technologies.
2. Description of the Related Art
MOS transistors are important components of semiconductor devices and the electrical performance of the gate of MOS transistors directly affects the quality of these devices. The gate region of an MOS transistor typically comprises a polycrystalline silicon (polysilicon) layer or an amorphous silicon layer used as main conducting layer, and sometimes a silicide layer, for example a layer of cobalt (Co) silicide, stacked on the main conducting layer. Likewise, the source and drain active regions of an MOS transistor comprise a doped silicon layer that may be covered with a silicide layer. These silicide layers provide good ohmic contact and consequently reduce the layer resistances of the MOS transistor and increase the operational speed of the semiconductor device that incorporates it.
Depending on the requirements of the application, it may thus be necessary to silicide the gate, drain and/or source regions of certain MOS transistors and not to silicide the corresponding regions of the other transistors produced on the wafer. This is because it may be necessary, for example, to reduce the contact resistances of certain transistors, while on the contrary to protect certain other transistors from electrostatic discharges by a high contact resistance.
In the prior art, it is conventional to use a mask for preventing a silicide forming on the regions not to be silicided. This mask may be formed from a stack comprising, on the one hand, an oxide layer, for example a layer of silicon dioxide (SiO2) obtained by CVD (Chemical Vapor Deposition) from tetraethyl orthosilicate (TEOS) and, on the other hand, a nitride layer, for example a layer of silicon nitride (Si3N4). Such a mask is sometimes called a “Si-Protect” mask in the jargon of those skilled in the art. The silicide does not form on the regions protected by this mask.
However, the formation of such a mask requires a thermal budget that is not very compatible with the junctions in 90 nm technology and in smaller technology. In addition, it generates stresses in the MOS transistors. Finally, it requires in itself a relatively large number of steps. In particular, it requires a deoxidation step before deposition of the cobalt (Co) in order to remove the SiO2 stop layer, which step results in an undesirable hollowing-out of the STI (Shallow Trench Isolation) trenches.